Through the analysis of data of AETA (a system of earthquake precursory signals), before and after Jiuzhaigou Ms 7.0 earthquake in Sichuan Province on August 8, 2017, the result shows that there were 13 AETA stations which captured the associated abnormalities of 36 AETA stations stalled in Sichuan Province, and 9 of which were close related. A typical wave (SRSS wave) of electronic-magnetic disturbance average value found in 11 stations of the 13 stations, had a feature of changing synchronously with the time of sunrise and sunset. An abnormal stripe was found before and after Jiuzhaigou earthquake by PCAETA algorithm applied in SRSS of the 11 stations. Furthermore, the abnormal stripe is also found in Mianning Disaster Prevention and Mitigation Bureau station during August 12 to November 20, in 2017. It is concluded that AETA system can capture close related precursory abnormalities at multiple stations before earthquake and the abnormal stripe of SRSS wave is an obvious and specific earthquake precursory characteristics.

An asynchronous low power RSA circuit structure and its modular multiplication circuit structure for smart cards and RFID tags are proposed. By using GTECH optimization scheme and BrzCallMux implementation strategy, ASIC implementation is carried out based on a TSMC 130 nm standard CMOS technology. Experimental results show that the area of the proposed asynchronous low power RSA is only 4% of that of another asynchronous RSA, its average time to perform a cryptographic operation is only 0.216% of that of another asynchronous RSA, and its power consumption is only 16.99% of that of its corresponding synchronous counterpart.

An improved model is proposed based on the transient power law model under Human Body Model (HBM) stress. This model can predict the gate oxide breakdown statistically under HBM stress. Through HSPICE simulation tool, the corresponding DC effective voltage on the MOS can be calculated. The scatter chart of the precharge voltage of the HBM circuit with the effective DC voltages of the MOS shows a linear relationship. Using the Laplace transform, the linear relationship is proved. Compared with the existing transient power law model, the improved model reduces the computational complexity under the HBM stress and is easier to predict the MOS gate oxide breakdown statistically. The proposed model provides an important reference for the evaluation of the reliability of the MOS gate oxide under the impact of HBM.

The authors introduce the multi-component seismic monitoring system AETA (acoustic & electromagnetic testing all in one system). The results of experiments in Yunnan, Sichuan, Tibet, Hebei, Beijing and Guangdong prove that the system AETA has the proper sensitivity with low cost and is easy to be installed. Meanwhile, the raw data and feature data refined from raw data have a good indication of earthquake. More subsequent experiments will be organized in west of China, capital circle of China and Taiwan Strait for deep research on effect of prediction.

Based on the existing equivalent formula of the transmission line pulse (TLP) and IEC 61000-4-2 stresses, the authors propose an analysis method of the system-level model with TLP stress as an input. Compared with the traditional analysis method under system-level IEC stress, the proposed method solves the issue that the calculation of the residual energy flowing into the device under test (DUT) is not accurate enough. Meanwhile, the prediction ability for the failure of the DUT is promoted. This work predicts the failure of the DUT under the mentioned two stresses through SPICE simulation. Furthermore, this work shows the validation through the measured results of the relevant printed circuit boards (PCBs), which confirms the promotion of the aforesaid prediction ability.

A low-power automatic gain control (AGC) strategy for BD-II/GPS compatible satellite navigation receivers is proposed. The proposed mixed-signal AGC has 55 dB gain control range and a simplified control loop. By monitoring the ADC sampling result, the proposed AGC automatically controlvariable gain amplifier (VGA) and programmable gain amplifiers (PGA). Compared with traditional counterpart, the proposed AGC strategy is more power-efficient, since it does not need a power detector or rectifier. The chip is fabricated in a TSMC 0.18 μm CMOS process and the measure results show that the settling time of AGC is within 1 ms, and it consumes only 2 mA current at 1.8 V power supply.

A volumetric display system based on FPGA and DLP technologies is raised. FPGA is used to construct the graphical processing unit, controlling and propagating video streams synthesized after image dithering and layer combined algorithms. This video stream is passed down inside the FPGA through SD card controlling unit, DDR2 high speed memory control, pixel frame converter and HDMI high resolution signal transmitting modules. Afterwards, the video stream is captured by the receiving end of the DLP projector, inside the projector’s video decoding module, the digital electrical signal is converted to light signal and projected to a spinning display underneath. This method allows the viewer perceiving a multi-angled 3D image hovering in air without the wearing of special glasses.

According to the hardware Trojans inserted during design and fabrication, the authors provide a new model of Trojan. New model is based on a finite state machine which is more difficult to trigger and detect than those based on combinational circuits. Also, the locations in target circuits to insert Trojans are considered to avoid being detected using path delay fingerprint method. S349 circuit from ISCAS’89 benchmark circuits is chosen as the target circuit. Functional simulations are performed and delay information is simulated. The results show that this type of hardware Trojan is difficult to activate and the insertion method is effective to hide delay information.

For solving the problem of human and vehicles classification in complex scene, a novel method based on multi-granularity perception SVM (support vector machine) is proposed. Firstly, motion regions of the video are detected and analyzed, and visual perception information is extracted by corner detection in motion regions. In order to reduce the noise interference, perception information is inferenced by Kalman filter in time-space domain. Furthermore, multi-granularity perception features of objects are constructed with the mass center of motion regions. Finally, a two-level SVM classifier is constructed, and classification results are obtained by training and classifying on the SVM classifier with multi-granularity perception features vector set. The results of experimentation show that the proposed method is good. The average correct rate of all-day classification between human and vehicles is up to 93.6% separately, and it is valid to avoid the influence of illumination, colors and object’s size variation. It is suitable for intelligent traffic system.

The authors propose a top-down design process for MASH21 modulator. In system level, coefficient scaling is used to limit integrator’s output; in circuit level, integrator transient modeling is used to analyze the effect caused by OP’s non-ideality, and get the optimized design region for SNR, area and power. A MASH21 modulator for digital audio application is designed to verify the proposed design criteria. This experimental prototype is implemented with TSMC18MMRF, operates under a single 1.8 V power supply, and achieves a measured SNDR of 91dB.

A coarse-grain reconfigurable processor ReMAP-2 is proposed for video codec applications which shares several important characteristics: compute intensity, parallelism, and locality. ReMAP-2 comprises of a reconfigurable array of processing elements and interconnect network with neighborly connect and segment buses, which possesses good scalability. The architecture can change the function of processing elements and the data path of the reconfigurable array by uploading different configuration stream for different applications, which is suit for multiple standard of video codec. The simulation result shows that ReMAP-2 can achieve much better performance than common media processors. The compute capability is close to or same as ASIC implementation and meanwhile it has upstanding flexibility.

An ultra-low power passive UHF RFID transponder complying with ISO/IEC 18000-6B protocol is presented. In order to provide an accurate clock for the digital baseband processing, an ultra-low power and self-calibrated clock generator is designed and implemented in the transponder with a clock variation within 4% against temperature from -50℃ to 120 ℃ or supply voltage from 0.7 to 1.6 V. Total power consumption of the novel clock generator is only 364 nW with 0.7V supply voltage. Further, a low voltage bandgap reference which generates 0.96 V with 100 nA current consumption is introduced. In digital baseband, clock gating and module reuse strategies are employed to further reduce the power consumption to 1.17 μW. This design is fabricated in 0.18 μm mix-signal CMOS process with a die size of 0.75 mm×0.75 mm. Measurement results show that the proposed RFID transponder operates with a sensitivity of -10 dBm.

The authors present a control scheme for UWModem with embedded processor in FPGA. The scheme builds system structure by choosing suitable communication bus type, and designs rational soft/ hardware cooperating procedure and interrupt controlling signals. The results from soft/hardware co-verification with MicroBlaze soft processor in Xilinx VirtexIV FPGA show that the control scheme can efficiently manager the whole digital signal processing in UWModem and report the situation in real-time with steady performance.

A hierarchically modularized design based clock accurate simulator platform ReSim is proposed for the flexible interconnection, expandability and dense computational characteristics of reconfigurable processor ReMAP. The simulator is designed under three hierarchy software framework, which contains interconnect modules to accelerate various interconnection architecture evaluation, control modules to simulate different compute model. The simulator can quickly establish the reconfigurable processor model and test the function validity of processor architecture, as well as evaluating the performance under the control of clock driving module for the whole system. The result shows that ReSim can support the evaluation and simulation of the reconfigurable processor architecture ReMAP-2 effectively.

The authors propose an optimizing method for the energy detector based on the parallel correlators in the time domain. With a method named as two-step correlation method and time sharing techniques, all the 1023 chip phases are detected in parallel. When the sampling frequency is 16. 368 MHz, the total correlator number is reduced to be 1/ 102. 3 of the non-optimized counterpart. Furthermore, the energy detector using the proposed method is implemented by FPGA and synthesized with Design Compiler. The test results show that when pre-detection time is 2s, C/N₀ = 21 dB-Hz, and false alarm is 0. 097% , the detection probability is as high as 90% .

A novel encoding scheme with high speed and low power is proposed for folding and interpolating ADC. In the encoder,XOR-OR encoding algorithmand a novel serial-parallel Domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has about 56% decrease on power delay product compared to conventional ROMencoder and this encoder is more applicable for the folding and interpolating ADC with higher resolution.

To design an AES coprocessor used on the mode of WSN(wireless sensor network), a method of reusing some given modules or other resources is presented. Also, a novel circuit of mixcolumn module is designed to reduce the whole area of the system. Some methods such as insulation of the operands, dynamic power management and optimization of coding are adopted to reduce the power consumption. The AES coprocessor on the node of WSN of this paper is integrated in Virtex4 FPGA, and meets all the requirements of WSN.

The authors analyze the detailed process of calculator schedule in high speed FIR (finite impose response) digital filter with add-and-shift algorithm based on FPGA (field programmable gate array). Different calculation situations and related schedule schemes are discussed and a clear rule of optimization is proposed. At last, an example of a 16-order FIR filter is implemented on Xilinx Spartan 3 3s1000ft256 FPGA platform. The occupied resource is 11.7% less than the one generated without optimization and/or 29.7% less than the one generated by Xinlinx Coregen^TM with distribute arithmetic (DA), respectively.

A current-sensing circuit using senseFETs as current sensing devices in a current mode PWM DC-DC Converter system is presented.It is easy to be integrated because of the simple structure and it owns excellent frequency response, low power dissipation.The accuracy of this circuit is high in a wide range of the load current，and it will be elevated with the using of the cascade-common-gate amplifiers' structure.The test chip is fabricated in CSMC 0.5 μm 2p3M 3.3 V CMOS process.The measurement results show that the buck converter can operate from 1.2 to 2 MHz with supply voltage from 2.5 to 5.5 V for lithium ion battery application，and the output voltage is 1.5 V.The highest accuracy of proposed current sensing circuit is 97.75% for the load current from 50 to 600 mA.

A low-dropout (LDO) voltage regulator with on-chip output capacitor for SoC applications is presented. The right-half-plane (RHP) zero generated by the gate-drain parasitic capacitance of the LDO pass element can be removed by a novel bi-directional asymmetric buffer (BDAB). This RHP zero removal scheme can enhance the stability, increase the unit-gain frequency (UGF) and improve the transient response performance. Post-layout simulation results of the proposed LDO show that the phase margin is better than 55°, the UGF is up to 1.7 MHz, while the overshoot and undershoot of the output voltages are less than 100 mV when the load current changes at a rate of 50 mA/μs.